Application Specific Scalable Architectures for Advanced Encryption Standard (AES) Algorithm

The work presented proposes two diverse FPGA based architectures with high-speed and low area constraints for suitable implementation of Advanced Encryption Standard (AES). The main focus of this paper is to compare different design architectures existing in literature with the proposed ones, based on application specific constraints. The high speed design presented here proposes a good engineering solution to high speed applications where area constraint can not be totally neglected. The high speed design manages to achieve a reasonable 6 Gbps throughput despite of the fact that it only covers mere 5800 slices in area .Low area architecture achieves a decent throughput of 1.98 Mbps with low slices count of 297. Some common applications of high speed design include broadband switches and firewall, whereas the low area design mainly focuses on compact applications like PDAs and cell phone in which area and power constraints are critical. Both the designs are implemented and tested using a Xilinx Spartan-III (XC3S2000) target device. Key-Words: Advanced Encryption Standard (AES), Subpipelined, High Speed, Low Area, Unrolled architecture, Cryptography, Throughput, FPGA, and Data Encryption Standard (DES).